
package decoderstage

import chisel3._
import chisel3.util._
class GRFReadBus extends Bundle{
  val rs = UInt(5.W)
  val rt = UInt(5.W)
}
class GRFDataBus extends Bundle{
  val rsData = UInt(32.W)
  val rtData = UInt(32.W)
}
class GRFWriteBus extends  Bundle{
  val PC = UInt(32.W)
  val writeID = UInt(5.W)
  val writeEnable = Bool()
  val writeData = UInt(32.W)
}
class GRF extends Module{
  val io = IO(new Bundle{
    val grfReadBus = Input(new GRFReadBus)
    val grfDataBus = Output(new GRFDataBus)
    val grfWriteBus = Input(new GRFWriteBus)
  })
  val rs = io.grfReadBus.rs
  val rt = io.grfReadBus.rt
  val rsData = io.grfDataBus.rsData
  val rtData = io.grfDataBus.rtData
  val writeID = io.grfWriteBus.writeID
  val writeEnable = io.grfWriteBus.writeEnable
  val writeData = io.grfWriteBus.writeData

  val grfs = RegInit(VecInit(Seq.fill(32){0.U(32.W)}))
  grfs(0) := DontCare
  rsData := MuxCase(grfs(rs),Seq(
    (rs === 0.U) -> 0.U,
    (rs === writeData && writeEnable) -> writeData
  ))
  rtData := MuxCase(grfs(rt),Seq(
    (rt === 0.U) -> 0.U,
    (rt === writeData && writeEnable) -> writeData
  ))
  val PC = io.grfWriteBus.PC
  when(writeEnable && writeID =/= 0.U){
    grfs(writeID) := writeData
    printf(p"PC=0x${Hexadecimal(PC)} ${grfs(writeID)} <= ${writeData}")
  }
}
